Addressing mode
Addressing modes are an aspect of the instruction set architecture in most central processing unit designs. Addressing modes define how the machine language instructions in that architecture identify the operand of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.
In computer programming, addressing modes are primarily of interest to those who write in assembly languages and to compiler writers. For a related concept see orthogonal instruction set which deals with the ability of any instruction to use any addressing mode.
Caveats
There are no generally accepted names for addressing modes: different authors and computer manufacturers may give different names to the same addressing mode, or the same names to different addressing modes. Furthermore, an addressing mode which, in one given architecture, is treated as a single addressing mode may represent functionality that, in another architecture, is covered by two or more addressing modes. For example, some complex instruction set computer architectures, such as the Digital Equipment Corporation VAX, treat registers and literal or immediate constants as just another addressing mode. Others, such as the IBM System/360 and its successors, and most reduced instruction set computer designs, encode this information within the instruction. Thus, the latter machines have three distinct instruction codes for copying one register to another, copying a literal constant into a register, and copying the contents of a memory location into a register, while the VAX has only a single "MOV" instruction. To confuse matters further: some processors such as the Microchip Technology PIC microcontrollers make no distinction between registers and memory.The term "addressing mode" is itself subject to different interpretations: either "memory address calculation mode" or "operand accessing mode". Under the first interpretation, instructions that do not read from memory or write to memory are considered not to have an "addressing mode". The second interpretation allows for machines such as VAX which use operand mode bits to allow for a register or for a literal operand. Only the first interpretation applies to instructions such as "load effective address," which loads the address of the operand, not the operand itself.
The addressing modes listed below are divided into code addressing and data addressing. Most computer architectures maintain this distinction, but there are some architectures which allow all addressing modes to be used in any context.
The instructions shown below are purely representative in order to illustrate the addressing modes, and do not necessarily reflect the mnemonics used by any particular computer.
Some computers, e.g., IBM 709, RCA 3301, do not have a single address mode field but rather have separate fields for indirect addressing and indexing.
Number of addressing modes
Computer architectures vary greatly as to the number of addressing modes they provide in hardware. There are some benefits to eliminating complex addressing modes and using only one or a few simpler addressing modes, even though it requires a few extra instructions, and perhaps an extra register. It has proven much easier to design pipelined CPUs if the only addressing modes available are simple ones.Most RISC architectures have only about five simple addressing modes, while CISC architectures such as the DEC VAX have over a dozen addressing modes, some of which are quite complicated. The IBM System/360 architecture has only four addressing modes; a few more have been added for the ESA/390 architecture.
When there are only a few addressing modes, the particular addressing mode required is usually encoded within the instruction code
. But when there are many addressing modes, a specific field is often set aside in the instruction to specify the addressing mode. The DEC VAX allowed multiple memory operands for almost all instructions, and so reserved the first few bits of each operand specifier to indicate the addressing mode for that particular operand.
Keeping the addressing mode specifier bits separate from the opcode operation bits produces an orthogonal instruction set.
Even on a computer with many addressing modes, measurements of actual programs indicate that the simple addressing modes listed below account for some 90% or more of all addressing modes used. Since most such measurements are based on code generated from high-level languages by compilers, this reflects to some extent the limitations of the compilers being used.
Load effective address
Some instruction set architectures, such as IBM System/360 and its successors, Intel x86, and the Motorola 68000 series, have a load effective address instruction. This calculates the effective operand address and loads it into a register, without accessing the memory it refers to. This can be useful when passing the address of an array element to a subroutine. It may also be a clever way of doing more calculations than normal in one instruction; for example, using such an instruction with the addressing mode "base+index+offset" allows one instruction to add two registers and a constant together and store the result in a third register.A few instruction set architectures, such as the Motorola 68000 series, also have a push effective address instruction. This calculates the effective operand address and pushes it on the stack rather than storing it in a register. This can be used to pass pointers as arguments to a function.
Simple addressing modes for code
Some simple addressing modes for code are shown below. The nomenclature may vary depending on platform.Absolute or direct
+----+------------------------------+|jump| address |
+----+------------------------------+
The effective address for an absolute instruction address is the address parameter itself with no modifications.
PC-relative
+----+------------------------------+|jump| offset | jump relative
+----+------------------------------+
The effective address for a PC-relative instruction address is the offset parameter added to the address of the next instruction. This offset is usually signed to allow reference to code both before and after the instruction.
This is particularly useful in connection with jump instructions, because typical jumps are to nearby instructions. Measurements of actual programs suggest that an 8 or 10 bit offset is large enough for some 90% of conditional jumps. For jumps to instructions that are not nearby, other addressing modes are used.
Another advantage of PC-relative addressing is that the code may be position-independent, i.e. it can be loaded anywhere in memory without the need to adjust any addresses.
Register indirect
+-------+-----+|jumpVia| reg |
+-------+-----+
The effective address for a register indirect instruction is the address in the specified register. For example, to access the content of address register A7.
The effect is to transfer control to the instruction whose address is in the specified register.
Many RISC machines, as well as the CISC IBM System/360 and successors, have subroutine call instructions that place the return address in an address register—the register indirect addressing mode is used to return from that subroutine call.
Sequential addressing modes for code
Sequential execution
+------+| nop | execute the following instruction
+------+
The CPU, after executing a sequential instruction, immediately executes the following instruction.
Sequential execution is not considered to be an addressing mode on some computers.
Most instructions on most CPU architectures are sequential instructions. Because most instructions are sequential instructions, CPU designers often add features that deliberately sacrifice performance on the other instructions—branch instructions—in order to make these sequential instructions run faster.
Conditional branches load the PC with one of 2 possible results, depending on the condition—most CPU architectures use some other addressing mode for the "taken" branch, and sequential execution for the "not taken" branch.
Many features in modern CPUs—instruction prefetch and more complex pipelineing, out-of-order execution, etc.—maintain the illusion that each instruction finishes before the next one begins, giving the same final results, even though that's not exactly what happens internally.
Each "basic block" of such sequential instructions exhibits both temporal and spatial locality of reference.
CPUs that do not use sequential execution
CPUs that do not use sequential execution with a program counter are extremely rare. In some CPUs, each instruction always specifies the address of next instruction. Such CPUs have an instruction pointer that holds that specified address; it is not a program counter because there is no provision for incrementing it. Such CPUs include some drum memory computers such as the IBM 650, the SECD machine, Librascope RPC 4000, and the RTX 32P.On processors implemented with horizontal microcode, the microinstruction may contain the high order bits of the next instruction address.
Other computing architectures go much further, attempting to bypass the von Neumann bottleneck using a variety of alternatives to the program counter.