Motorola 68000 series


The Motorola 68000 series is a family of 32-bit complex instruction set computer microprocessors. During the 1980s and early 1990s, they were popular in personal computers and workstations and were the primary competitors of Intel's x86 microprocessors. They were best known as the processors used in the early Apple Macintosh, the Sharp X68000, the Commodore Amiga, the Sinclair QL, the Atari ST and Falcon, the Atari Jaguar, the Sega Genesis and Sega CD, the Philips CD-i, the Capcom System I, the AT&T UNIX PC, the Tandy Model 16/16B/6000, the Sun Microsystems Sun-1, Sun-2 and Sun-3, the NeXT Computer, NeXTcube, NeXTstation, and NeXTcube Turbo, early Silicon Graphics IRIS workstations, the Aesthedes, computers from MASSCOMP, the Texas Instruments TI-89/TI-92 calculators, the Palm Pilot, the Control Data Corporation CDCNET Device Interface, the VTech Precomputer Unlimited and the Space Shuttle. Although no modern desktop computers are based on processors in the 680x0 series, derivative processors are still widely used in embedded systems.
Motorola ceased development of the 680x0 series architecture in 1994, replacing it with the PowerPC RISC architecture, which was developed in conjunction with IBM and Apple Computer as part of the AIM alliance.

Family members

68020:
68030:
  • Split instruction and data cache of 256 bytes each
  • On-chip memory management unit
  • Low cost EC = No MMU
  • Burst Memory Interface
68040:
68060:

Uses

The 680x0 line of processors has been used in a variety of systems, from high-end Texas Instruments calculators to all of the members of the Palm Pilot series that run Palm OS 1.x to 4.x, and even radiation-hardened versions in the critical control systems of the Space Shuttle.
The 680x0 CPU family became most well known for powering desktop computers and video game consoles such as the Macintosh 128K, Amiga, Sinclair QL, Atari ST, Genesis / Mega Drive, NG AES/Neo Geo CD, CDTV. They were the processors of choice in the 1980s for Unix workstations and servers such as AT&T's UNIX PC, Tandy's Model 16/16B/6000, Sun Microsystems' Sun-1, Sun-2, Sun-3, NeXT Computer, Silicon Graphics, and numerous others.
The Saturn uses the 68000 for audio processing and other I/O tasks, while the Jaguar includes a 68000 intended for basic system control and input processing, but was frequently used for running game logic. Many arcade boards also use 68000 processors including those from Capcom, SNK, and Sega.
The first several versions of Adobe's PostScript interpreters were 68000-based. The 68000 in the Apple LaserWriter and LaserWriter Plus was clocked faster than the version used then in Macintosh computers. A fast 68030 in later PostScript interpreters, including the standard resolution LaserWriter IIntx, IIf and IIg, the higher resolution LaserWriter Pro 600 series and the very high resolution Linotronic imagesetters, the 200PS and 300PS. Thereafter, Adobe generally preferred a RISC for its processor, as its competitors, with their PostScript clones, had already gone with RISCs, often an AMD 29000-series. The early 68000-based Adobe PostScript interpreters and their hardware were named for Cold War-era U.S. rockets and missiles: Atlas, Redstone, etc.
Microcontrollers derived from the 68000 family have been used in a huge variety of applications. CPU32 and ColdFire microcontrollers have been manufactured in the millions as automotive engine controllers.
Many proprietary video editing systems used 68000 processors, such as the MacroSystem Casablanca, which was a black box with an easy to use graphic interface. It was intended for the amateur and hobby videographer market. It is also worth noting its earlier, bigger and more professional counterpart, the "DraCo". The groundbreaking Quantel Paintbox series of early based 24-bit paint and effects system was originally released in 1981 and during its lifetime it used nearly the entire range of 68000 family processors, with the sole exception of the 68060, which was never implemented in its design. Another contender in the video arena, the Abekas 8150 DVE system, used the 680EC30, and the Play Trinity, later renamed Globecaster, uses several 68030s. The Bosch FGS-4000/4500 Video Graphics System manufactured by Robert Bosch Corporation, later BTS, used a 68000 as its main processor; it drove several others to perform 3D animation in a computer that could easily apply Gouraud and Phong shading. It ran a modified Motorola VERSAdos operating system.

Architecture

People who are familiar with the PDP-11 or VAX usually feel comfortable with the 68000 series. With the exception of the split of general-purpose registers into specialized data and address registers, the 68000 architecture is in many ways a 32-bit PDP-11.
It had a more orthogonal instruction set than those of many processors that came before and after. That is, it was typically possible to combine operations freely with operands, rather than being restricted to using certain addressing modes with certain instructions. This property made programming relatively easy for humans, and also made it easier to write code generators for compilers.
The 68000 series has eight 32-bit general-purpose data registers, and eight address registers. The last address register is the stack pointer, and assemblers accept the label SP as equivalent to A7.
In addition, it has a 16-bit status register. The upper 8 bits is the system byte, and modification of it is privileged. The lower 8 bits is the user byte, also known as the condition code register, and modification of it is not privileged. The 68000 comparison, arithmetic, and logic operations modify condition codes to record their results for use by later conditional jumps. The condition code bits are "zero", "carry", "overflow", "extend", and "negative". The "extend" flag deserves special mention, because it is separate from the carry flag. This permits the extra bit from arithmetic, logic, and shift operations to be separated from the carry for flow-of-control and linkage.
While the 68000 had a 'supervisor mode', it did not meet the Popek and Goldberg virtualization requirements due to the single instruction 'MOVE from SR', which copies the status register to another register, being unprivileged but sensitive. In the Motorola 68010 and later, this was made privileged, to better support virtualization software.
The 68000 series instruction set can be divided into the following broad categories:
The Motorola 68020 added some new instructions that include some minor improvements and extensions to the supervisor state, several instructions for software management of a multiprocessing system, some support for high-level languages which did not get used much, bigger multiply and divide instructions, and bit field manipulations.
The standard addressing modes are:
  • Register direct
  • *Data register, e.g. "D0"
  • *Address register, e.g. "A0"
  • Register indirect
  • *Simple address, e.g.
  • *Address with post-increment, e.g. +
  • *Address with pre-decrement, e.g. −
  • *Address with a 16-bit signed offset, e.g. 16
  • *Register indirect with index register and 8-bit signed offset e.g. 8 or 8
  • :For + and −, the actual increment or decrement value is dependent on the operand size: a byte access adjusts the address register by 1, a word by 2, and a long by 4.
  • PC relative with displacement
  • *Relative 16-bit signed offset, e.g. 16. This mode was very useful for position-independent code.
  • *Relative with 8-bit signed offset with index, e.g. 8
  • Absolute memory location
  • *Either a number, e.g. "$4000", or a symbolic name translated by the assembler
  • *Most assemblers used the "$" symbol for hexadecimal, instead of "0x" or a trailing H.
  • *There were 16 and 32-bit versions of this addressing mode
  • Immediate mode
  • *Data stored in the instruction, e.g. "#400"
  • Quick immediate mode
  • *3-bit unsigned with value stored in opcode
  • *In addq and subq, 0 is the equivalent to 8
  • *e.g. moveq #0,d0 was quicker than clr.l d0
Plus: access to the status register, and, in later models, other special registers.
The Motorola 68020 added a scaled indexing address mode, and added another level of indirection to many of the pre-existing modes.
Most instructions have dot-letter suffixes, permitting operations to occur on 8-bit bytes, 16-bit words, and 32-bit longs.
Most instructions are dyadic, that is, the operation has a source, and a destination, and the destination is changed. Notable instructions were:
  • Arithmetic: ADD, SUB, MULU, MULS, DIVU, DIVS, NEG, and CMP
  • Binary-coded decimal arithmetic: ABCD, NBCD, and SBCD
  • Logic: EOR, AND, NOT, OR
  • Shifting: LSL, LSR, ASR, ASL, ROXL, ROXR, ROL, ROR
  • Bit test and manipulation in memory or data register: BSET, BCLR, BCHG and BTST. All of these instructions first test the destination bit and set the CCR Z bit if the destination bit is 0, respectively.
  • Multiprocessing control: TAS, test-and-set, performed an indivisible bus operation, permitting semaphores to be used to synchronize several processors sharing a single memory
  • Flow of control: JMP, JSR, BSR, RTS, RTE, TRAP, CHK
  • Branch: Bcc. Of the remaining two possible conditions, always true and always false, BRA has a separate mnemonic, and BSR takes the encoding that would otherwise have been 'branch never'.
  • Decrement-and-branch: DBcc, which, provided the condition was false, decremented the low word of a D-register and, if the result was not -1, branched to a destination. This use of −1 instead of 0 as the terminating value allowed the easy coding of loops that had to do nothing if the count was 0 to start with, with no need for another check before entering the loop. This also facilitated nesting of DBcc.