Apollo Guidance Computer


The Apollo Guidance Computer was a digital computer produced for the Apollo program that was installed on board each Apollo command module and Apollo Lunar Module. The AGC provided computation and electronic interfaces for guidance, navigation, and control of the spacecraft. The AGC was the first computer based on silicon integrated circuits. The computer's performance was comparable to the first generation of home computers from the 1970s, such as the Kenbak-1, Apple II, TRS-80, and Commodore PET. At around in size, the AGC held 4,100 IC packages.
The AGC has a 16-bit word length, with 15 data bits and one parity bit. Most of the software on the AGC is stored in a special read-only memory known as core rope memory, fashioned by weaving wires through and around magnetic cores, though a small amount of read/write core memory is available.
Astronauts communicated with the AGC using a numeric display and keyboard called the DSKY. The AGC and its DSKY user interface were developed in the early 1960s for the Apollo program by the MIT Instrumentation Laboratory and first flew in 1966. The onboard AGC systems were secondary, as NASA conducted primary navigation with mainframe computers in Houston.

Operation

In the earlier Project Gemini program, the astronauts flew manually with control sticks. In the Apollo program however, the flight was controlled by the computer. The astronauts flew manually briefly during lunar landings. Each Moon flight carried two AGCs, one each in the command module and the Apollo Lunar Module, with the exception of Apollo 7 which was an Earth orbit mission and Apollo 8 which did not need a lunar module for its lunar orbit mission. The AGC in the command module was the center of its guidance, navigation and control system. The AGC in the lunar module ran its Apollo PGNCS, with the acronym pronounced as pings.
Each lunar mission had two additional computers:
The AGC was designed at the MIT Instrumentation Laboratory under Charles Stark Draper, with hardware design led by Eldon C. Hall. Early architectural work came from J. H. Laning Jr., Albert Hopkins, Richard Battin, Ramon Alonso, and Hugh Blair-Smith.
The flight hardware was fabricated by Raytheon, whose Herb Thaler was also on the architectural team.
According to Kurinec et al., the chips were welded onto the boards rather than soldered as might be expected. Apollo Guidance Computer logic module drawings specify resistance-welding.

Logic hardware

Following the use of integrated circuit chips in the Interplanetary Monitoring Platform in 1963, IC technology was later adopted for the AGC. The Apollo flight computer was one of the first computers to use silicon IC chips.
While the Block I version used 4,100 ICs, each containing a single three-input NOR gate, the later Block II version used about 2,800 ICs, mostly dual three-input NOR gates and smaller numbers of expanders and sense amplifiers. The ICs, from Fairchild Semiconductor, were implemented using resistor–transistor logic in a flat-pack. They were connected via wire wrap, and the wiring was then embedded in cast epoxy plastic.
The use of a single type of IC throughout the AGC avoided problems that plagued another early IC computer design, the Minuteman II guidance computer, which used a mix of diode–transistor logic and diode logic gates. NOR gates are universal logic gates from which any other gate can be made, though at the cost of using more gates.

Memory

The computer had 2,048 words of erasable magnetic-core memory and 36,864 words of read-only core rope memory. Both had cycle times of 11.72 microseconds. The memory word length was 16 bits: 15 bits of data and one odd-parity bit. The CPU-internal 16-bit word format was 14 bits of data, one overflow bit, and one sign bit.

DSKY interface

The user interface to the AGC was the DSKY, standing for display and keyboard and usually pronounced . It has an array of indicator lights, numeric displays, and a calculator-style keyboard. Commands were entered numerically, as two-digit numbers: Verb and Noun. Verb described the type of action to be performed and Noun specified which data were affected by the action specified by the Verb command.
Each digit was displayed via a green high-voltage electroluminescent seven-segment display; these were driven by electromechanical relays, limiting the update rate. Three five-digit signed numbers could also be displayed in octal or decimal, and were typically used to display vectors such as space craft attitude or a required velocity change. Although data was stored internally in metric units, they were displayed as United States customary units. This calculator-style interface was the first of its kind.
The command module has two DSKYs connected to its AGC: one located on the main instrument panel and a second located in the lower equipment bay near a sextant used for aligning the inertial guidance platform. The lunar module had a single DSKY for its AGC. A flight director attitude indicator, controlled by the AGC, was located above the DSKY on the commander's console and on the LM.

Timing

The AGC timing reference came from a 2.048 MHz crystal clock. The clock was divided by two to produce a four-phase 1.024 MHz clock which the AGC used to perform internal operations. The 1.024 MHz clock was also divided by two to produce a 512 kHz signal called the master frequency; this signal was used to synchronize external Apollo spacecraft systems.
The master frequency was further divided through a scaler, first by five using a ring counter to produce a 102.4 kHz signal. This was then divided by two through 17 successive stages called F1 through F17. The F10 stage was fed back into the AGC to increment the real-time clock and other involuntary counters using Pinc. The F17 stage was used to intermittently run the AGC when it was operating in the standby mode.

Central registers

The AGC had four 16-bit registers for general computational use, called the central registers:
  • A: The accumulator, for general computation
  • Z: The program counter – the address of the next instruction to be executed
  • Q: The remainder from the DV instruction, and the return address after TC instructions
  • LP: The lower product after MP instructions
There were also four locations in core memory, at addresses 20–23, dubbed editing locations because whatever was stored there would emerge shifted or rotated by one bit position, except for one that shifted right seven bit positions, to extract one of the seven-bit interpretive op. codes that were packed two to a word. This was common to Block I and Block II AGCs.

Other registers

The AGC had additional registers that were used internally in the course of operation:
  • S: 12-bit memory address register, the lower portion of the memory address
  • Bank/Fbank: 4-bit ROM bank register, to select the 1 kiloword ROM bank when addressing in the fixed-switchable mode
  • Ebank: 3-bit RAM bank register, to select the 256-word RAM bank when addressing in the erasable-switchable mode
  • Sbank : 1-bit extension to Fbank, required because the last 4 kilowords of the 36-kiloword ROM was not reachable using Fbank alone
  • SQ: 4-bit sequence register; the current instruction
  • G: 16-bit memory buffer register, to hold data words moving to and from memory
  • X: The 'x' input to the adder or the increment to the program counter
  • Y: The other input to the adder
  • U: Not really a register, but the output of the adder
  • B: General-purpose buffer register, also used to pre-fetch the next instruction. At the start of the next instruction, the upper bits of B were copied to SQ, and the lower bits were copied to S.
  • C: Not a separate register, but the ones' complement of the B register
  • IN: Four 16-bit input registers
  • OUT: Five 16-bit output registers

    Instruction set

The instruction format used 3 bits for opcode, and 12 bits for address. Block I had 11 instructions: TC, CCS, INDEX, XCH, CS, TS, AD, and MASK, and SU, MP, and DV. The first eight, called basic instructions, were directly accessed by the 3-bit op. code. The final three were denoted as extracode instructions because they were accessed by performing a special type of TC instruction immediately before the instruction.
The Block I AGC instructions consisted of the following:
;TC : An unconditional branch to the address specified by the instruction. The return address was automatically stored in the Q register, so the TC instruction could be used for subroutine calls.
;CCS : A complex conditional branch instruction. The A register was loaded with data retrieved from the address specified by the instruction. The diminished absolute value of the data was then computed and stored in the A register. If the number was greater than zero, the DABS decrements the value by 1; if the number was negative, it is complemented before the decrement is applied—this is the absolute value. Diminished means "decremented but not below zero". Therefore, when the AGC performs the DABS function, positive numbers will head toward plus zero, and so will negative numbers but first revealing their negativity via the four-way skip below. The final step in CCS is a four-way skip, depending upon the data in register A before the DABS. If register A was greater than 0, CCS skips to the first instruction immediately after CCS. If register A contained plus zero, CCS skips to the second instruction after CCS. Less than zero causes a skip to the third instruction after CCS, and minus zero skips to the fourth instruction after CCS. The primary purpose of the count was to allow an ordinary loop, controlled by a positive counter, to end in a CCS and a TC to the beginning of the loop, equivalent to an IBM 360's BCT. The absolute value function was deemed important enough to be built into this instruction; when used for only this purpose, the sequence after the CCS was TC *+2, TC *+2, AD ONE. A curious side effect was the creation and use of CCS-holes when the value being tested was known to be never positive, which occurred more often than one might suppose. That left two whole words unoccupied, and a special committee was responsible for assigning data constants to these holes.
;INDEX: Add the data retrieved at the address specified by the instruction to the next instruction. INDEX can be used to add or subtract an index value to the base address specified by the operand of the instruction that follows INDEX. This method is used to implement arrays and table look-ups; since the addition was done on both whole words, it was also used to modify the op. code in a following instruction, and on rare occasions both functions at once.
;RESUME: A special instance of INDEX. This is the instruction used to return from interrupts. It causes execution to resume at the interrupted location.
;XCH : Exchange the contents of memory with the contents of the A register. If the specified memory address is in fixed memory, the memory contents are not affected, and this instruction simply loads register A. If it is in erasable memory, overflow "correction" is achieved by storing the leftmost of the 16 bits in A as the sign bit in memory, but there is no exceptional behavior like that of TS.
;CS : Load register A with the ones' complement of the data referenced by the specified memory address.
;TS : Store register A at the specified memory address. TS also detects, and corrects for, overflows in such a way as to propagate a carry for multi-precision add/subtract. If the result has no overflow, nothing special happens; if there is overflow, the leftmost one goes the memory as the sign bit, register A is changed to +1 or −1 accordingly, and control skips to the second instruction following the TS. Whenever overflow is a possible but abnormal event, the TS was followed by a TC to the no-overflow logic; when it is a normal possibility, the TS is followed by CAF ZERO to complete the formation of the carry into the next higher-precision word. Angles were kept in single precision, distances and velocities in double precision, and elapsed time in triple precision.
;AD : Add the contents of memory to register A and store the result in A. The 2 leftmost bits of A may be different before and/or after the AD. The fact that overflow is a state rather than an event forgives limited extents of overflow when adding more than two numbers, as long as none of the intermediate totals exceed twice the capacity of a word.
;MASK: Perform a bit-wise and of memory with register A and store the result in register A.
;MP : Multiply the contents of register A by the data at the referenced memory address and store the high-order product in register A and the low-order product in register LP. The parts of the product agree in sign.
;DV : Divide the contents of register A by the data at the referenced memory address. Store the quotient in register A and the absolute value of the remainder in register Q. Unlike modern machines, fixed-point numbers were treated as fractions, so you could produce garbage if the divisor was not larger than the dividend; there was no protection against that situation. In the Block II AGC, a double-precision dividend started in A and L, and the correctly signed remainder was delivered in L. That considerably simplified the subroutine for double precision division.
;SU : Subtract the data at the referenced memory address from the contents of register A and store the result in A.
Instructions were implemented in groups of 12 steps, called timing pulses. The timing pulses were named TP1 through TP12. Each set of 12 timing pulses was called an instruction subsequence. Simple instructions, such as TC, executed in a single subsequence of 12 pulses. More complex instructions required several subsequences. The multiply instruction used 8 subsequences: an initial one called MP0, followed by an MP1 subsequence which was repeated 6 times, and then terminated by an MP3 subsequence. This was reduced to 3 subsequences in Block II.
Each timing pulse in a subsequence could trigger up to 5 control pulses. The control pulses were the signals which did the actual work of the instruction, such as reading the contents of a register onto the bus, or writing data from the bus into a register.