I2C

I²C, alternatively known as I2C and IIC, is a synchronous, multi-master/multi-slave, single-ended, serial communication bus invented in 1980 by Philips Semiconductors. It is widely used for attaching lower-speed peripheral integrated circuits to processors and microcontrollers in short-distance, intra-board communication.
In the European Patent EP0051332B1 Ad P.M.M. Moelands and Herman Schutte are named as inventors of the I2C bus. Both were working in 1980 as development engineers in the central application laboratory CAB of Philips in Eindhoven, where the I2C bus was developed as "Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations". The US patent was granted under number. The internal development name of the bus was first COMIC, which was later changed to I2C. The patent was transferred by both gentlemen to Koninklijke Philips NV.
The I²C bus can be found in a wide range of electronics applications where simplicity and low manufacturing cost are more important than speed. PC components and systems which involve I²C include serial presence detect EEPROMs on dual in-line memory modules and Extended Display Identification Data for monitors via VGA, DVI, and HDMI connectors. Common I²C applications include reading hardware monitors, sensors, real-time clocks, controlling actuators, accessing low-speed DACs and ADCs, controlling simple LCD or OLED displays, changing computer display settings via Display Data Channel, and changing speaker volume.
A particular strength of I²C is the capability of a microcontroller to control a network of device chips with just two general-purpose I/O pins. Many other bus technologies used in similar applications, such as Serial Peripheral Interface Bus, require more pins and signals to connect multiple devices.
System Management Bus, defined by Intel and Duracell in 1994, is a subset of I²C, defining a stricter usage. One purpose of SMBus is to promote robustness and interoperability. Accordingly, modern I²C systems incorporate some policies and rules from SMBus, sometimes supporting both I²C and SMBus, requiring only minimal reconfiguration either by commanding or output pin use. System management for PC systems uses SMBus, whose pins are allocated in both conventional PCI and PCI Express connectors.

Design

I²C patents and specifications used the terms master/slave between 1980 and 2021. In 2021, revision 7 of the I²C specification changed the terms to controller/target. The technical definitions of such devices, and their roles on an I²C bus, remain unchanged.File:I2C controller-target.svg|thumb|An example schematic with one controller, three target nodes, and pull-up resistors R_p
I²C uses only two signals: serial data line and serial clock line. Both are bidirectional and pulled up with resistors. Typical voltages used are +5 V or +3.3 V, although systems with other voltages are permitted.
The I²C [|reference design] has a 7-bit address space, with a rarely used 10-bit extension. Common I²C bus speeds are the standard mode and the fast mode. There is also a low-speed mode, but arbitrarily low clock frequencies are also allowed. Later revisions of I²C can host more nodes and run at faster speeds. These speeds are more widely used on embedded systems than on PCs.
Note that the bit rates are quoted for the transfers between controller and target without clock stretching or other hardware overhead. Protocol overheads include a target address and perhaps a register address within the target device, as well as per-byte ACK/NACK bits. Thus the actual transfer rate of user data is lower than those peak bit rates alone would imply. For example, if each interaction with a target inefficiently allows only 1 byte of data to be transferred, the data rate will be less than half the peak bit rate.
The number of nodes that can exist on a given I²C bus is limited by the address space and also by the total bus capacitance of 400 pF, which restricts practical communication distances to a few meters. The relatively high impedance and low noise immunity require a common ground potential, which again restricts practical use to communication within the same PC board or small system of boards.

Mode	Maximum speed	Maximum capacitance	Drive	Direction
Standard mode		400 pF	Open drain*	Bidirectional
Fast mode		400 pF	Open drain*	Bidirectional
Fast mode plus		550 pF	Open drain*	Bidirectional
High-speed mode		400 pF	Open drain*	Bidirectional
High-speed mode		100 pF	Open drain*	Bidirectional
Ultra-fast mode		?	Push–pull	Unidirectional

Message protocols

I²C defines basic types of transactions, each of which begins with a START and ends with a STOP:

Single message where a controller writes data to a target.
Single message where a controller reads data from a target.
Combined format, where a controller issues at least two reads or writes to one or more targets.

In a combined transaction, each read or write begins with a START and the target address. The START conditions after the first are also called repeated START bits. Repeated STARTs are not preceded by STOP conditions, which is how targets know that the next message is part of the same transaction.
Any given target will only respond to certain messages, as specified in its product documentation.
Pure I²C systems support arbitrary message structures. SMBus is restricted to nine of those structures, such as read word N and write word N, involving a single target. PMBus extends SMBus with a Group protocol, allowing multiple such SMBus transactions to be sent in one combined message. The terminating STOP indicates when those grouped actions should take effect. For example, one PMBus operation might reconfigure three power supplies, and their new configurations would take effect at the same time: when they receive that STOP.
With only a few exceptions, neither I²C nor SMBus define message semantics, such as the meaning of data bytes in messages. Message semantics are otherwise product-specific. Those exceptions include messages addressed to the I²C general call address or to the SMBus Alert Response Address; and messages involved in the SMBus Address Resolution Protocol for dynamic address allocation and management.
In practice, most targets adopt request-response control models, where one or more bytes following a write command are treated as a command or address. Those bytes determine how subsequent written bytes are treated or how the target responds on subsequent reads. Most SMBus operations involve single-byte commands.

Messaging example: 24C32 EEPROM

One specific example is the 24C32 type EEPROM, which uses two request bytes that are called Address High and Address Low. These bytes are used for addressing bytes within the 32 kbit EEPROM address space. The same two-byte addressing is also used by larger EEPROMs, like the 24C512, which stores 512 kbits. Writing data to and reading from these EEPROMs uses a simple protocol: the address is written, and then data is transferred until the end of the message. The data transfer part of the protocol can cause trouble on the SMBus, since the data bytes are not preceded by a count, and more than 32 bytes can be transferred at once. I²C EEPROMs smaller than 32 kbit, like the 2 kbit 24C02, are often used on the SMBus with inefficient single-byte data transfers to overcome this problem.
A single message writes to the EEPROM. After the START, the controller sends the chip's bus address with the direction bit clear, then sends the two-byte address of data within the EEPROM and then sends data bytes to be written starting at that address, followed by a STOP. When writing multiple bytes, all the bytes must be in the same 32-byte page. While it is busy saving those bytes to memory, the EEPROM will not respond to further I²C requests.
To read starting at a particular address in the EEPROM, a combined message is used. After a START, the controller first writes that chip's bus address with the direction bit clear and then the two bytes of EEPROM data address. It then sends a START and the EEPROM's bus address with the direction bit set. The EEPROM will then respond with the data bytes beginning at the specified EEPROM data address — a combined message: first a write, then a read. The controller issues an ACK after each read byte except the last byte, and then issues a STOP. The EEPROM increments the address after each data byte transferred; multi-byte reads can retrieve the entire contents of the EEPROM using one combined message.

Physical layer

At the physical layer, both SCL and SDA lines are an open-drain or open-collector bus design, thus a pull-up resistor is needed for each line. A logic "0" is output by pulling the line to ground, and a logic "1" is output by letting the line float so that the pull-up resistor pulls it high. A line is never actively driven high. This wiring allows multiple nodes to connect to the bus without short circuits from signal contention. High-speed systems may use a current source instead of a resistor to pull up only SCL or both SCL and SDA, to accommodate higher bus capacitance and enable faster rise times.
An important consequence of this is that multiple nodes may be driving the lines simultaneously. If any node is driving the line low, it will be low. Nodes that are trying to transmit a logical one can detect this and conclude that another node is active at the same time.
When used on SCL, this is called clock stretching and is a flow-control mechanism for targets. When used on SDA, this is called arbitration and ensures that there is only one transmitter at a time.
When idle, both lines are high. To start a transaction, SDA is pulled low while SCL remains high. It is illegal to transmit a stop marker by releasing SDA to float high again, so the next step is to pull SCL low.
Except for the start and stop signals, the SDA line only changes while the clock is low; transmitting a data bit consists of pulsing the clock line high while holding the data line steady at the desired level.
While SCL is low, the transmitter sets SDA to the desired value and lets SCL float high. The controller then waits for SCL to actually go high; this will be delayed by the finite rise time of the SCL signal and may be additionally delayed by a target's clock stretching.
Once SCL is high, the controller waits a minimum time to ensure that the receiver has seen the bit, then pulls it low again. This completes transmission of one bit.
After every 8 data bits in one direction, an "acknowledge" bit is transmitted in the other direction. The transmitter and receiver switch roles for one bit, and the original receiver transmits a single "0" bit back. If the transmitter sees a "1" bit instead, it learns that:

The target is unable to accept the data. No such target, command not understood, or unable to accept any more data.
The controller wishes the transfer to stop after this data byte.

Only the SDA line changes direction during acknowledge bits; the SCL is always controlled by the controller.
After the acknowledge bit, the clock line is low and the controller may do one of three things:

Begin transferring another byte of data: the transmitter sets SDA, and the controller pulses SCL high.
Send a "Stop": Set SDA low, let SCL go high, then let SDA go high. This releases the I²C bus.
Send a "Repeated start": Set SDA high, let SCL go high, then pull SDA low again. This starts a new I²C bus message without releasing the bus.