Asynchronous circuit


Asynchronous circuit is a sequential digital logic circuit that does not use a global clock circuit or signal generator to synchronize its components. Instead, the components are driven by a handshaking circuit which indicates a completion of a set of instructions. Handshaking works by simple data transfer protocols. Many synchronous circuits were developed in early 1950s as part of bigger asynchronous systems. Asynchronous circuits and theory surrounding is a part of several steps in integrated circuit design, a field of digital electronics engineering.
Asynchronous circuits are contrasted with synchronous circuits, in which changes to the signal values in the circuit are triggered by repetitive pulses called a clock signal. Most digital devices today use synchronous circuits. However asynchronous circuits have a potential to be much faster, have a lower level of power consumption, electromagnetic interference, and better modularity in large systems. Asynchronous circuits are an active area of research in digital logic design.
It was not until the 1990s when viability of the asynchronous circuits was shown by real-life commercial products.

Overview

All digital logic circuits can be divided into combinational logic, in which the output signals depend only on the current input signals, and sequential logic, in which the output depends both on current input and on past inputs. In other words, sequential logic is combinational logic with memory. Virtually all practical digital devices require sequential logic. Sequential logic can be divided into two types, synchronous logic and asynchronous logic.

Synchronous circuits

In synchronous logic circuits, an electronic oscillator generates a repetitive series of equally spaced pulses called the clock signal. The clock signal is supplied to all the components of the IC. Flip-flops only flip when triggered by the edge of the clock pulse, so changes to the logic signals throughout the circuit begin at the same time and at regular intervals. The output of all memory elements in a circuit is called the state of the circuit. The state of a synchronous circuit changes only on the clock pulse. The changes in signal require a certain amount of time to propagate through the combinational logic gates of the circuit. This time is called a propagation delay.
, timing of modern synchronous ICs takes significant engineering efforts and sophisticated design automation tools. Designers have to ensure that clock arrival is not faulty. With the ever-growing size and complexity of ICs it's a challenging task. In huge circuits, signals sent over clock distribution network often end up at different times at different parts. This problem is widely known as "clock skew".
The maximum possible clock rate is capped by the logic path with the longest propagation delay, called the critical path. Because of that, the paths that may operate quickly are idle most of the time. A widely distributed clock network dissipates a lot of useful power and must run whether the circuit is receiving inputs or not. Because of this level of complexity, testing and debugging takes over half of development time in all dimensions for synchronous circuits.

Asynchronous circuits

The asynchronous circuits do not need a global clock, and the state of the circuit changes as soon as the inputs change. The local functional blocks may be still employed but the clock skew problem still can be tolerated.
Since asynchronous circuits do not have to wait for a clock pulse to begin processing inputs, they can operate faster. Their speed is theoretically limited only by the propagation delays of the logic gates and other elements.
However, asynchronous circuits are more difficult to design and subject to problems not found in synchronous circuits. This is because the resulting state of an asynchronous circuit can be sensitive to the relative arrival times of inputs at gates. If transitions on two inputs arrive at almost the same time, the circuit can go into the wrong state depending on slight differences in the propagation delays of the gates. This is called a race condition. In synchronous circuits this problem is less severe because race conditions can only occur due to inputs from outside the synchronous system, called asynchronous inputs.
Although some fully asynchronous digital systems have been built, today asynchronous circuits are typically used in a few critical parts of otherwise synchronous systems where speed is at a premium, such as signal processing circuits.

Theoretical foundation

The original theory of asynchronous circuits was created by David E. Muller in mid-1950s. This theory was presented later in the well-known book "Switching Theory" by Raymond Miller.
The term "asynchronous logic" is used to describe a variety of design styles, which use different assumptions about circuit properties. These vary from the bundled delay model – which uses "conventional" data processing elements with completion indicated by a locally generated delay model – to delay-insensitive design – where arbitrary delays through circuit elements can be accommodated. The latter style tends to yield circuits which are larger than bundled data implementations, but which are insensitive to layout and parametric variations and are thus "correct by design".

Asynchronous logic

Asynchronous logic is the logic required for the design of asynchronous digital systems. These function without a clock signal and so individual logic elements cannot be relied upon to have a discrete true/false state at any given time. Boolean logic is inadequate for this and so extensions are required.
Since 1984, Vadim O. Vasyukevich developed an approach based upon new logical operations which he called venjunction and sequention. This takes into account not only the current value of an element, but also its history.
Karl M. Fant developed a different theoretical treatment of asynchronous logic in his work Logically determined design in 2005 which used four-valued logic with null and intermediate being the additional values. This architecture is important because it is quasi-delay-insensitive. Scott C. Smith and Jia Di developed an ultra-low-power variation of Fant's Null Convention Logic that incorporates multi-threshold CMOS. This variation is termed Multi-threshold Null Convention Logic, or alternatively Sleep Convention Logic.

Petri nets

s are an attractive and powerful model for reasoning about asynchronous circuits. A particularly useful type of interpreted Petri nets, called Signal Transition Graphs, was proposed independently in 1985 by Leonid Rosenblum and Alex Yakovlev and Tam-Anh Chu. Since then, STGs have been studied extensively in theory and practice, which has led to the development of popular software tools for analysis and synthesis of asynchronous control circuits, such as Petrify and Workcraft.
Subsequent to Petri nets other models of concurrency have been developed that can model asynchronous circuits including the Actor model and process calculi.

Benefits

A variety of advantages have been demonstrated by asynchronous circuits. Both quasi-delay-insensitive circuits and less pure forms of asynchronous circuitry which use timing constraints for higher performance and lower area and power present several advantages.
  • Robust and cheap handling of metastability of arbiters.
  • Average-case performance: an average-case time of operation is not limited to the worst-case completion time of component as it is in synchronous circuits. This results in better latency and throughput performance. Examples include speculative completion which has been applied to design parallel prefix adders faster than synchronous ones, and a high-performance double-precision floating point adder which outperforms leading synchronous designs.
  • * Early completion: the output may be generated ahead of time, when result of input processing is predictable or irrelevant.
  • * Inherent elasticity: variable number of data items may appear in pipeline inputs at any time. This contributes to high performance while gracefully handling variable input and output rates due to unclocked pipeline stages delays.
  • * No need for timing-matching between functional blocks either. Though given different delay models this depends on actual approach of asynchronous circuit implementation.
  • * Freedom from the ever-worsening difficulties of distributing a high-fan-out, timing-sensitive clock signal.
  • * Circuit speed adapts to changing temperature and voltage conditions rather than being locked at the speed mandated by worst-case assumptions.
  • Lower, on-demand power consumption; zero standby power consumption. In 2005 Epson has reported 70% lower power consumption compared to synchronous design. Also, clock drivers can be removed which can significantly reduce power consumption. However, when using certain encodings, asynchronous circuits may require more area, adding similar power overhead if the underlying process has poor leakage properties.
  • *No need for power-matching between local asynchronous functional domains of circuitry. Synchronous circuits tend to draw a large amount of current right at the clock edge and shortly thereafter. The number of nodes switching drops off rapidly after the clock edge, reaching zero just before the next clock edge. In an asynchronous circuit, the switching times of the nodes does not correlated in this manner, so the current draw tends to be more uniform and less bursty.
  • Robustness toward transistor-to-transistor variability in the manufacturing transfer process, variations of voltage supply, temperature, and fabrication process parameters.
  • Less severe electromagnetic interference. Synchronous circuits create a great deal of EMI in the frequency band at their clock frequency and its harmonics; asynchronous circuits generate EMI patterns which are much more evenly spread across the spectrum.
  • Design modularity, improved noise immunity and electromagnetic compatibility. Asynchronous circuits are more tolerant to process variations and external voltage fluctuations.